Field of the Invention
The present invention relates to an image processing apparatus which transfers image data to a memory such as a DRAM, and a method for controlling the image processing apparatus.
Description of the Related Art
In an image processing apparatus that is used in imaging apparatuses such as a digital camera, image processing such as pixel interpolation, white balance, sharpness, noise reduction and reduction/expansion is performed. For instance, there is a multi-rate signal processing, as one example of noise reduction processing. This processing is a technology of dividing image data into a plurality of frequency bands to create plural types of image data, then subjecting each piece of image data to appropriate filtering processing, and subjecting the image data which has been processed for each frequency band to a frequency synthesizing process again. In such processing, the frequency of access to the memory increases for the reading and writing of the plural types of image data, and in order to reduce a processing time period, image data needs to be efficiently transferred to the memory.
A DRAM (Dynamic Random Access Memory) is generally used as a memory for storing image data therein. The DRAM has a plurality of banks, and in the case where different row addresses (different pages) in the same bank are accessed, a pre-charge command (page close) and an active command (page open) needs to be issued. While these commands are executed, the same bank cannot be accessed. For this reason, the more the frequency of access to different pages in the same bank (frequency of page switching) becomes, the more the pre-charge command and the active command need to be issued, which causes a problem that the access efficiency to the DRAM results in decreasing.
Conventionally, with respect to the problem as described above, such a data transfer method has been proposed as to decrease the frequency of page switching as much as possible to reduce the frequency of the pre-charge, and enhance the efficiency of access to the DRAM. For instance, Japanese Patent No. 3688977 discloses a technology of reducing the frequency of pre-charge, by making image data of a plurality of lines having an equal row address continuously be accessed, when image data of the plurality of lines is accessed, which are stored in the memory.
However, in the case where the noise reduction processing using the multi-rate signal processing as described above is continuously performed on image data of a plurality of frames, plural types of image data need to be read from and written in the memory at the same time. In addition, for instance, in the case where the image data needs to be processed in a determined order when the plural types of image data are written in and read out from the memory, it is difficult to make the line having an equal row address in the same bank in the DRAM to be continuously accessed, as in the technology which has been conventionally disclosed. Accordingly, in the noise reduction processing using the multi-rate signal processing which requires complex memory access, there is such a problem that random-access occurs in different pages in the same bank, and access efficiency for the DRAM decreases.